CSE Seminar: FireSim and FirePerf: Simulating, Debugging, and Profiling RTL Designs with Cloud FPGAs

Speaker Name
Sagar Karandikar
Speaker Title
PhD student in Computer Science
Speaker Organization
University of California, Berkeley
Start Time
End Time
via Zoom presentation
Scott Beamer


This talk covers FireSim (https://fires.im), an open-source FPGA-accelerated hardware simulation platform, and FirePerf, a recently released set of tools that enable high-fidelity, out-of-band performance profiling of FireSim-simulated designs. This talk will discuss both our research goals in building FireSim (simulating warehouse-scale systems from the ground-up), as well as its value for the broader open hardware community. FireSim automatically instruments and transforms RTL designs into fast (10s-100s MHz), deterministic, FPGA-based simulators that enable productive pre silicon verification and performance validation. Unlike FPGA prototypes, FireSim includes synthesizable and timing accurate models for standard I/O interfaces like DRAM, Ethernet, UART, and others, allowing users to obtain accurate performance measurements for their design, pre-silicon. FireSim also provides a large array of design debugging features not available in FPGA prototypes, including assertion synthesis and printf synthesis, while also simplifying the process of integrating vendor-provided logic-analyzer tools. FireSim also includes FirePerf, a set of out-of-band profiling tools that enable cross-stack hardware/software co-design of simulated designs using out-of-band instruction tracing, performance counter recording, and Flame Graph integration. These tools enable rapidly introspecting on a design deep into simulation time. Using a distributed Ethernet network model, FireSim also supports simulating scale-out systems, including cycle-accurate simulations of thousand-node datacenters hosted on hundreds of cloud FPGAs working in concert. To construct a system to simulate, users can plug their own designs into FireSim or harness the included in-order and out-of-order RISC-V cores, uncore components, peripherals, and accelerators to compose a complex RISC-V SoC to simulate via the Chipyard SoC framework. FireSim also includes a software generation tool, FireMarshal, which automates the process of building complex Linux-based workloads for RISC-V systems simulated in FireSim. By supporting AWS EC2 F1 as a host platform, FireSim also removes the high capex traditionally involved in large-scale FPGA-based simulation, democratizing access to realistic pre-silicon hardware modeling of new designs.


Sagar Karandikar is a PhD student in Computer Science at the University of California, Berkeley, focusing in Computer Architecture and Systems. He works in the Berkeley Architecture Research group and the ADEPT and RISE Labs, advised by Krste Asanovic. His research focuses on hardware/software co-design in warehouse-scale machines. He leads the FireSim project, which enables scalable cycle-accurate simulation of hardware designs on FPGAs in the cloud. His work on FireSim has been selected as an IEEE Micro Top Pick and nominated for CACM Research Highlights.

*Zoom link:   https://ucsc.zoom.us/j/92528497331

Event Type