CSE Seminar: New Intermediate Representation Designs for Live Hardware Development and Hardware Description Language Integration

Speaker Name
Sheng-Hong Wang
Speaker Title
Ph.D. Student in Computer Science and Engineering
Speaker Organization
University of California, Santa Cruz
Start Time
End Time
via Zoom presentation
Jose Renau


The hardware development cycle is prolonged and tedious compared to the faster design turnaround time of the software development model. In Microarchitecture Santa Cruz group, we have built a ""live"" hardware development flow called LiveHD. The ultimate goal of LiveHD is to provide design feedback in a few seconds with the designer's preferred hardware description languages (HDLs). Prior work of LiveHD uses the LGraph as the intermediate representation (IR) to express the netlist. In the advancement thesis, we first present the new LGraph IR enhancements. Our new memory map library is now used in LGraph to enables fast load/unload LGraph from/to the disk. LGraph also adds the support of hierarchical traversal and attribute features, which allows the integrated tools to execute their algorithm engine hierarchically.

Two bottlenecks in the LiveHD framework still potentially hinder our goal in achieving live feedback with HDLs. First, LiveHD only interfaces one HDL, System Verilog, by using Yosys. Second, LiveHD uses LGraph as the internal low-level IR, but the semantic gap between high-level modern HDLs and the LGraph IR makes it hard to interface directly. We further propose a language-neutral abstract syntax tree (LNAST) to address these problems. LNAST is a tree-based IR that bridges modern HDLs into LiveHD; it is a higher-level representation of a design than LGraph. LGraph and LNAST  representations will be seamlessly converted to each other. As a high-level IR, LNAST can capture high-level semantics from different HDLs in the common tree structure. This enables HDLs to leverage the live synthesis and simulation framework in LiveHD. Another key motivation for designing LNAST is the generation of human-readable C++ and HDLs, which will be essential infrastructure for our future research projects of hardware simulation and Pyrope compiler verification.


Sheng-Hong Wang is currently working toward a Ph.D. degree in Computer Science and Engineering at University of California, Santa Cruz. Before joining UCSC, Sheng-Hong worked as an advanced digital circuit designer at Novatek for 5 years. His current research focus includes Compiler/EDA tools for productive hardware design and Computer Architecture. Sheng-Hong received his BS and MS degree in Electrical Engineering from National Cheng Kung University in 2010 and 2012.

*Zoom link: https://ucsc.zoom.us/j/92528497331



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