The ever-increasing design complexity will soon far exceed what many existing static timing analysis (STA) tools are able to scale with reasonable design time and effort. A key fundamental challenge is that STA must incorporate new parallel paradigms comprising manycore central processing units (CPUs) and graphics processing units (GPUs) to allow transformational performance. Parallelizing STA on a heterogeneous architecture is extremely challenging because the data access patterns on circuit graphs are inherently irregular. In this talk, we introduce new algorithms to parallelize two important STA tasks, graph analysis and path analysis, on a heterogeneous architecture. Our algorithms enable efficient parallel decomposition strategies between CPU and GPU tasks. We have implemented our algorithms in the open-source STA engine, OpenTimer, and shown up 500x speed-up over existing timers in analyzing large designs. In many cases, our algorithm with one GPU is even faster than that of 40 CPUs.
Dr. Huang is an assistant professor in the Department of ECE at the University of Utah. He has been working on parallel algorithms and systems for EDA, and created several award-winning open-source software, such as Taskflow, OpenTimer, and DtCraft. His software is being used by many people.
Zoom Link: https://ucsc.zoom.us/j/9314278