Defense: A Fast, Parallel, and Multi-Languages Hardware Compilation Framework

Sheng-Hong Wang
Computer Engineering PhD Candidate
Location
Hybrid
Advisor
Jose Renau

Join us in-person: Engineering 2, Room 215

Join us on Zoom: https://ucsc.zoom.us/j/99803728846?pwd=UXlVaHR1eUF6c202dU03MHhvMExJQT09 / Passcode: 819710

Description: A set of new Hardware Description Languages (HDLs) with a higher level of expressiveness has emerged to ease the difficulty of depicting complex hardware design. However, the increased compilation time also becomes a new bottleneck on the designer’s productivity and adds more burden to the already lengthy hardware EDA flow. Mean-while, these new HDLs tend to be developed with a stand-alone compiler, making an HDL compilation innovation hard to share with the compiler community.

I design and implement LiveHD, a new multi-threaded, fast, and generic compilation framework across many HDLs (FIRRTL, Verilog, and Pyrope). Internally, a high-level generic AST-like IR, LNAST, is used to interface the front-end source languages. Then LiveHD translate the LNAST-IR into a low-level LGraph IR, which carries most of the compilation passes and optimizations. I propose new parallel full and bottom-up passes to handle HDLs. The resulting compiler is able to parallelize all the compiler steps.

LiveHD can achieve 5.5x speedup scalability when elaborating a multicore RISC-V designed in the FIRRTL HDL. It also gets from 7.7x to 8.4x speedup scalability for a benchmark designed in all three HDLs. This is achieved with a fast single-threaded LiveHD baseline where it has 6x speedup compared to compilers such as Scala-FIRRTL and 8.6x against Yosys on Verilog. The highly parallelized and generic LiveHD compilation framework will open many exciting opportunities in the HDLs compiler and EDA research domain.