Advancement: A verification framework for timing side-channels in microprocessor designs

Ramesh Jayaraman
Computer Engineering Ph.D. Student
Location
Virtual Event
Advisor
Jose Renau

Join us on Zoomhttps://ucsc.zoom.us/j/98046817835?pwd=Tk9vRC80VnYvZXNkSTFSR0M3RncyUT09 / Passcode: 568957

Description: Since the advent of the modern microprocessor, the pursuit of better performance has led to increased design complexity. This increased complexity manifests due to adopting several design concepts like branch prediction, speculative execution, Out-of-Order execution, and their respective implementation choices. When implementing these design concepts in hardware, it is necessary to store information about the execution state of the processor in some form.

By design, multiple processes can run on the same hardware. This leads to the execution state of any given process being influenced by one or more other processes. This creates massive security vulnerabilities through timing side-channel attacks, the most infamous classes belonging to Spectre, MDS, and Foreshadow. These are flaws inherent in the nature of the aforementioned design concepts due to their need to maintain information about the execution state to deliver increased performance. These vulnerabilities are found in most deployed modern processors. Most attempts at fixing or patching them through software incur huge performance penalties and necessitate a hardware redesign to recoup these performance penalties.

This work presents novel techniques to be deployed during the design and verification of microprocessors that will utilize the timing and side-channel effects of these vulnerabilities to the designers' advantage to prove the existence of such vulnerabilities in designs that have been verified using conventional design methodologies. We demonstrate the incidence of timing and side-channel effects in two RISC-V designs, Ariane and BlackParrot.